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MCP2030A
Three-Channel Analog Front-End Device with 1 mVPP Input Detection Sensitivity
Device Features
* * * * Three input pins for analog input signals High input detection sensitivity (1 mVPP, typical) High modulation depth sensitivity (as low as 8%) Three output selections: - Demodulated data - Carrier clock - RSSI Input carrier frequency: 125 kHz, typical Input data rate: 10 Kbps, maximum Eight internal configuration registers Bidirectional transponder communication (LF talk back) Programmable antenna tuning capacitance (up to 63 pF, 1 pF/step) Programmable output-enable filter Low standby current: 6.5 A (with three channels enabled), typical Low operating current: 19 A (with three channels enabled), typical Serial Peripheral Interface (SPI) with external devices Supports Battery Backup mode and batteryless operation with external circuits Industrial and Extended Temperature Range: -40C to +85C (industrial)
Description
The MCP2030A is a stand-alone Analog Front-End (AFE) device for Low-Frequency (LF) sensing and bidirectional communication applications. The device has eight internal configuration registers. These registers, with the exception of the read-only Status register, are readable and programmable by an external device. The device has three low-frequency input channels. Each input channel can be individually enabled or disabled. The device can detect an input signal with amplitude as low as ~1 mVPP and can demodulate an amplitude-modulated input signal with as low as 8% modulation depth. The device can also transmit data by clamping and unclamping the input LC antenna voltage. The device can output demodulated data, carrier clock, or RSSI current, depending on the register setting. The demodulated data and carrier clock outputs are available on the LFDATA pin, while the RSSI output is available on the RSSI pin. The RSSI current output is linearly proportional to the input signal strength. The device has programmable internal tuning capacitors for each input channel. The user can program these capacitors up to 63 pF, 1 pF per step. These internal tuning capacitors can be used effectively for fine-tuning of the external LC resonant circuit. The device is optimized for very low current consumption and has various battery-saving low-power modes (Sleep, Standby, Active). The device can also be operated in Battery Backup and Batteryless modes using a few external components. This device is available in 14-pin PDIP, SOIC, and TSSOP packages.
* * * * * * * * * * *
Typical Applications
* Automotive industry applications: - Passive Keyless Entry (PKE) transponder - Remote door locks and gate openers - Engine immobilizer - LF initiator sensor for tire pressure monitoring systems * Security Industry applications: - Long range access control transponder - Parking lot entry transponder - Hands-free apartment door access - Asset control and management
Package Types
MCP2030A PDIP, SOIC, TSSOP VSS CS SCLK/ALERT RSSI LFDATA/ CCLK/SDIO VDD 1 2 3 4 NC 5 6 7 14 13 VSS LCCOM
12 NC LCX 11 10 9 8 LCY LCZ VDD
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MCP2030A
NOTES:
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MCP2030A
1.0 ELECTRICAL SPECIFICATIONS
Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings()
Ambient temperature under bias...................-40C to +125C Storage temperature .................................... -65C to +150C Voltage on VDD with respect to VSS ............... -0.3V to +6.5V Voltage on all other pins with respect to VSS ...................................... -0.3V to (VDD + 0.3V) Maximum current out of VSS pin .................................300 mA Maximum current into VDD pin ....................................250 mA Maximum LC Input Voltage (LCX, LCY, LCZ) loaded, with device........................ 10.0 VPP Maximum LC Input Voltage (LCX, LCY, LCZ) unloaded, without device............. 700.0 VPP Maximum Input Current (rms) into device per LC Channel.............................................................10 mA Human Body ESD rating ....................................2000 (min.) V Machine Model ESD rating ..................................200 (min.) V
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Operating temperature LC Signal Input Carrier Frequency LCCOM connected to VSS Parameters Supply Voltage VDD Start Voltage to ensure internal Power-on Reset (POR) signal Modulation Transistor-on Resistance Active Current (detecting signal) 1 LC Input Channel Receiving Signal 3 LC Input Channel Receiving Signals Standby Current (wait to detect signal) ISTDBY 1 LC Input Channel Enabled 2 LC Input Channels Enabled 3 LC Input Channels Enabled Sleep Current Analog Input Leakage Current LCX, LCY, LCZ LCCOM Digital Input Low Voltage Digital Input High Voltage Digital Input Leakage Current(3) SDI SCLK, CS Note 1: 2: 3: VIL VIH IIL -- -- -- -- 1 1 A A ISLEEP IAIL -- -- VSS 0.8 VDD -- -- -- -- 1 1 0.3 VDD VDD A A V V VDD = 3.6V, VSS VIN 1V with respect to ground. Internal tuning capacitors are switched off, tested in Sleep mode. SCLK, SDI, CS SCLK, SDI, CS VDD = 3.6V VSS VPIN VDD VPIN VDD -- -- -- -- 2 5 6.5 0.2 5 8 10.5 1 A A A A CS = VDD; ALERT = VDD Standard Operating Conditions (unless otherwise stated) -40C TA +85C Sinusoidal 300 mVPP 125 kHz Sym VDD VPOR RM IACT -- -- 10 19 -- 25 A A Min 2.0 -- -- Typ(2) 3.0 -- 50 Max 3.6 1.8 100 Units V V W VDD = 3.0V CS = VDD Input = Continuous Wave (CW); Amplitude = 300 mVPP. All channels enabled. CS = VDD; ALERT = VDD Conditions
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, +25C unless otherwise stated. These parameters are for design guidance only and are not tested. Negative current is defined as current sourced by the pin.
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MCP2030A
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Operating temperature LC Signal Input Carrier Frequency LCCOM connected to VSS Parameters Digital Output Low Voltage ALERT, LFDATA/SDIO Digital Output High Voltage ALERT, LFDATA/SDIO Digital Input Pull-Up Resistor CS, SCLK Note 1: 2: 3: These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, +25C unless otherwise stated. These parameters are for design guidance only and are not tested. Negative current is defined as current sourced by the pin. RPU VOH VDD - 0.5 50 -- 200 -- 350 V k IOH = -400 A, VDD = 2.0V VDD = 3.6V Standard Operating Conditions (unless otherwise stated) -40C TA +85C Sinusoidal 300 mVPP 125 kHz Sym Min Typ(2) Max Units Conditions Analog Front-End section -- -- VSS +0.4 V IOL = 1.0 mA, VDD = 2.0V
VOL
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MCP2030A
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Operating temperature LC Signal Input Carrier Frequency LCCOM connected to VSS Parameters Input Sensitivity Standard Operating Conditions (unless otherwise stated) -40C TA +85C Sinusoidal 300 mVPP 125 kHz Sym VSENSE -- 1 -- mVPP Min Typ(2) Max Units Conditions VDD = 3.0V Output-enable filter disabled, AGCSIG = 0; MODMIN = 00 (33% modulation depth setting) Input = Continuous Wave (CW) Output = Logic level transition from low-to-high at sensitivity level for CW input. Trimmed to 1 mVPP input sensitivity for all channels. VDD = 3.0V, Force IIN = 5 A (worst-case) VDD = 2.0V, VIN = 8 VDC VDD = 3.0V -- -- 0 -30 -- -- dB dB No sensitivity reduction selected Max reduction selected Monotonic increment in attenuation value from setting = 0000 to 1111 by design VDD = 3.0V -- -- -- -- FCARRIER FMOD -- -- 60 33 14 8 125 -- 84 49 26 -- -- 10 % % % % kHz kHz Input data rate with NRZ data format. VDD = 3.0V Minimum modulation depth setting= 33% Input conditions: Amplitude = 300 mVPP Modulation depth = 100% See Section 5.21 "Minimum Modulation Depth Requirement for Input Signal". See Modulation Depth Definition in Figure 5-5.
Coil de-Q-ing Voltage RF Limiter (RFLM) must be active RF Limiter Turn-on Resistance (LCX, LCY, LCZ) Sensitivity Reduction
VDE_Q RFLM SADJ
3 --
-- 300
5 700
V W
Minimum Modulation Depth 60% setting 33% setting 14% setting 8% setting Carrier frequency Input modulation frequency
VIN_MOD
Note 1: 2: 3: 4:
Parameter is characterized but not tested. Data in "Typ" column is at 3.0V, +25C unless otherwise stated. These parameters are for design guidance only and are not tested. Required output-enable filter high time must account for input path analog delays (= TOEH - TDR + TDF). Required output-enable filter low time must account for input path analog delays (= TOEL + TDR - TDF).
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MCP2030A
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Operating temperature LC Signal Input Carrier Frequency LCCOM connected to VSS Parameters LCX Tuning Capacitor Standard Operating Conditions (unless otherwise stated) -40C TA +85C Sinusoidal 300 mVPP 125 kHz Sym CTUNX -- 44 0 59 -- 82 pF pF Min Typ(2) Max Units Conditions VDD = 3.0V, Config. Reg. 1, bits <6:1> Setting = 000000 63 pF 30% Config. Reg. 1, bits <6:1> Setting = 111111 63 steps, approx. 1 pF/step Monotonic increment in capacitor value from setting = 000000 to 111111 by design LCY Tuning Capacitor CTUNY -- 44 0 59 -- 82 pF pF VDD = 3.0V, Config. Reg. 2, bits <6:1> Setting = 000000 63 pF 30% Config. Reg. 2, bits <6:1> Setting = 111111 63 steps, approx. 1 pF/step Monotonic increment in capacitor value from setting = 000000 to 111111 by design LCZ Tuning Capacitor CTUNZ -- 44 0 59 -- 82 pF pF VDD = 3.0V, Config. Reg. 3, bits<6:1> Setting = 000000 63 pF 30% Config. Reg. 3, bits<6:1> Setting = 111111 63 steps, approx. 1 pF/step Monotonic increment in capacitor value from setting = 000000 to 111111 by design Q of Internal Tuning Capacitors Demodulator Charge Time (delay time of demodulated output to rise) Q_C TDR 50(1) -- -- 50 -- -- s VDD = 3.0V Minimum modulation depth setting = 33% Input conditions: Amplitude = 300 mVPP Modulation depth = 100% VDD = 3.0V MOD depth setting = 33% Input conditions: Amplitude = 300 mVPP Modulation depth = 100% VDD 3.0V. Time is measured from 10% to 90% of amplitude
Demodulator Discharge Time (delay time of demodulated output to fall)
TDF
--
50
--
s
Rise time of LFDATA Note 1: 2: 3: 4:
TRLFDATA
--
0.5
--
s
Parameter is characterized but not tested. Data in "Typ" column is at 3.0V, +25C unless otherwise stated. These parameters are for design guidance only and are not tested. Required output-enable filter high time must account for input path analog delays (= TOEH - TDR + TDF). Required output-enable filter low time must account for input path analog delays (= TOEL + TDR - TDF).
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MCP2030A
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Operating temperature LC Signal Input Carrier Frequency LCCOM connected to VSS Parameters Fall time of LFDATA Standard Operating Conditions (unless otherwise stated) -40C TA +85C Sinusoidal 300 mVPP 125 kHz Sym TFLFDATA Min -- Typ(2) 0.5 Max -- Units s Conditions VDD 3.0V Time is measured from 10% to 90% of amplitude
AGC stabilization time (TAGC + TPAGC) AGC initialization time High time after AGC initialization time Gap time after AGC stabilization time Time element of pulse Time from exiting Sleep or POR to being ready to receive signal Minimum time AGC level must be held after receiving AGC Preserve command Internal RC oscillator frequency Inactivity timer time-out Alarm timer time-out LC Pin Input Resistance for LCX, LCY, LCZ pins LC Pin Input Parasitic Capacitance for LCX, LCY, LCZ pins Minimum output-enable filter high time OEH (Bits Config0<8:7>) 01 = 1 ms 10 = 2 ms 11 = 4 ms 00 = Filter Disabled Minimum output-enable filter low time OEL (Bits Config0<6:5>) 00 = 1 ms 01 = 1 ms 10 = 2 ms 11 = 4 ms Note 1: 2: 3: 4:
TSTAB TAGC TPAGC TGAP TE TRDY TPRES
4 -- -- 200 100 -- 5(1)
-- 3.5 62.5 -- -- -- --
-- -- -- -- -- 50
(1)
ms ms s s s ms ms AGC level must not change more than 10% during TPRES Internal clock trimmed at 32 kHz during test 512 cycles of RC oscillator @ FOSC 1024 cycles of RC oscillator @ FOSC LCCOM grounded, VDD = 3V, FCARRIER = 125 kHz LCCOM grounded, VDD = 3V, FCARRIER = 125 kHz RC oscillator = FOSC (see FOSC specification for variations). Viewed from the pin input(3) Minimum pulse width
--
FOSC TINACT TALARM RIN
27 13.5 27
32 16 32
35.5 17.75 35.5
kHz ms ms
-- CIN -- TOEH
800(1) 24(1)
-- --
k pF
32 (~1 ms) 64 (~2 ms) 128 (~4 ms) -- TOEL
-- -- -- --
-- -- -- --
clock count
RC oscillator = FOSC Viewed from the pin input(4) 32 (~1 ms) 32 (~1 ms) 64 (~2 ms) 128 (~4 ms) -- -- -- -- -- -- -- -- clock count
Parameter is characterized but not tested. Data in "Typ" column is at 3.0V, +25C unless otherwise stated. These parameters are for design guidance only and are not tested. Required output-enable filter high time must account for input path analog delays (= TOEH - TDR + TDF). Required output-enable filter low time must account for input path analog delays (= TOEL + TDR - TDF).
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DS22235B-page 7
MCP2030A
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Operating temperature LC Signal Input Carrier Frequency LCCOM connected to VSS Parameters Maximum output-enable filter period OEH 01 01 01 01 10 10 10 10 11 11 11 11 00 OEL 00 = 01 = 10 = 11 = 00 01 10 11 00 01 10 11 XX = = = = TOEH 1 ms 1 ms 1 ms 1 ms 2 ms 2 ms 2 ms 2 ms TOEL 1 ms (Filter 1) 1 ms (Filter 1) 1 ms (Filter 2) 1 ms (Filter 3) 1 ms (Filter 4) 1 ms (Filter 4) 2 ms (Filter 5) 4 ms (Filter 6) Standard Operating Conditions (unless otherwise stated) -40C TA +85C Sinusoidal 300 mVPP 125 kHz Sym TOET -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 96 (~3 ms) 96 (~3 ms) 128 (~4 ms) 192 (~6 ms) 128 (~4 ms) 128 (~4 ms) 160 (~5 ms) 250 (~8 ms) 192 (~6 ms) 192 (~6 ms) 256 (~8 ms) 320 (~10 ms) -- LFDATA output appears as long as input signal level is greater than VSENSE. A A A VIN = 30 mVPP VIN = 300 mVPP VIN = 3 VPP, VDD = 3.0V, Linearly increases with input signal amplitude. Tested at room temperature only (see Equation 5-1 and Figure 5-7 for test method). Min Typ(2) Max Units Conditions RC oscillator = FOSC
clock count
= 4 ms 1 ms (Filter 7) = 4 ms 1 ms (Filter 7) = 4 ms 2 ms (Filter 8) = 4 ms 4 ms (Filter 9) = Filter Disabled IRSSI
RSSI current output
-- -- --
3 30 250
-- -- --
RSSI current linearity
ILRRSSI
-15
--
15
%
Note 1: 2: 3: 4:
Parameter is characterized but not tested. Data in "Typ" column is at 3.0V, +25C unless otherwise stated. These parameters are for design guidance only and are not tested. Required output-enable filter high time must account for input path analog delays (= TOEH - TDR + TDF). Required output-enable filter low time must account for input path analog delays (= TOEL + TDR - TDF).
DS22235B-page 8
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MCP2030A
SPI TIMING
Electrical Specifications: Operating temperature LC Signal Input Carrier Frequency LCCOM connected to VSS Parameters SCLK Frequency CS fall to first SCLK edge setup time SDI setup time SDI hold time SCLK high time SCLK low time SDO setup time SCLK last edge to CS rise setup time CS high time CS rise to SCLK edge setup time SCLK edge to CS fall setup time Rise time of SPI data (SPI Read command) Fall time of SPI data (SPI Read command) Note 1: Standard Operating Conditions (unless otherwise stated) -40C TA +85C Sinusoidal 300 mVPP 125 kHz Sym FSCLK TCSSC TSU THD THI TLO TDO TSCCS TCSH TCS1 TCS0 TRSPI TFSPI Min -- 100 30 50 150 150 -- 100 500 50 50 -- -- Typ(1) -- -- -- -- -- -- -- -- -- -- -- 10 10 Max 3 -- -- -- -- -- 150 -- -- -- -- -- -- Units MHz ns ns ns ns ns ns ns ns ns ns ns ns SCLK edge when CS is high VDD 3.0V. Time is measured from 10% to 90% of amplitude VDD 3.0V. Time is measured from 90% to 10% of amplitude Conditions
Data in "Typ" column is at 3.0V, +25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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MCP2030A
NOTES:
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MCP2030A
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = -40C to +85C, VDD = 2.0V VDD 3.6V, VSS = 0V.
3.5 3 Current (A) 2.5 2 1.5 1 0.5 0 1.6
+125C
14 12
+85oC
+125oC
Current (A)
+85C
10 8 6 4 2 0
+25oC -40oC
+25C
-40C
2.1
2.6 3.1 VDD(V)
3.6
1.6
2.1
2.6 VDD(V)
3.1
3.6
Standby Current (1 Channel Enabled)
6 5 Current (A)
+85 C
o
Active Current (1 Channel Enabled)
18 16 14 Current (A) 12 10 8 6 4 2 0
+85oC +125oC
+125oC
4 3 2 1 0 1.6
+25 C
o
-40 C
o
+25oC
-40oC
2.1
2.6 VDD(V)
3.1
3.6
1.6
2.1
2.6 V DD(V)
3.1
3.6
Standby Current (2 Channels Enabled)
Active Current (2 Channels Enabled)
9 8 7 Current (A)
+25oC +85oC +125oC
25
+85 C
o
+125oC
20
Current (A)
6 5 4 3 2 1 0 1.6
-40oC
15
+25oC -40oC
10 5 0 1.6 2.1 2.6 VDD(V) 3.1 3.6
2.1
2.6 VDD(V)
3.1
3.6
Standby Current (3 Channels Enabled) FIGURE 2-1: Typical Standby Current.
Active Current (3 Channels Enabled) FIGURE 2-2: Typical Active Current.
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MCP2030A
Note: Unless otherwise indicated, TA = -40C to +85C, VDD = 2.0V VDD 3.6V, VSS = 0V.
12 De-Q'ed (Loaded) Coil Voltage (VPP) 10 8 6 4 2 0 0 200 400 600 Unloaded Coil Voltage (VPP) 800
Oscillator Frequency (kHz.)
35 34 33
Osc. Freq. @ VDD = 3.6V
32 31
Osc. Freq. @ VDD = 2.0V
30 29 -50 -25 0 25 50 75 100 125 Temperature (C)
FIGURE 2-3: Oscillator Frequency vs. Temperature, VDD = 3.6V and 2.0V.
50.0% 45.0% 40.0% 35.0% 30.0% 25.0% 20.0% 15.0% 10.0% 5.0% 0.0% Percentage of Occurences (%)
VDD = 2.0V -40C 25C 85C
FIGURE 2-6: De-Q-ed Voltage vs. Unloaded Coil Voltage.
80 70 60 Ohms 50 40 30 20 10 0
Ch. X Ch. Y Ch. Z
27
28
29
30
31
32
33
34
35
0
2 VDD (V)
4
6
Oscillator Frequency (kHz.)
FIGURE 2-4: Oscillator Frequency Histograms vs. Temperature, VDD = 2V.
FIGURE 2-7: Modulation Transistor-on Resistance (+25C).
70
50.0% 45.0% 40.0% 35.0% 30.0% 25.0% 20.0% 15.0% 10.0% 5.0% 0.0%
Percentage of Occurences (%)
VDD = 3.6V
Capacitance (pF)
-40C 25C 85C
60 50 40 30 20 10 0 0 20 40 60 80
Ch. X Ch. Y Ch. Z
27
28
29
30
31
32
33
34
35
Oscillator Frequency (kHz.)
Bit Setting (Steps)
FIGURE 2-5: Oscillator Frequency Histograms vs. Temperature at VDD = 3V.
FIGURE 2-8: Typical Tuned Capacitance Value vs. Configuration Register Bit Setting (VDD = 3V, Temperature = +25C).
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MCP2030A
Note: Unless otherwise indicated, TA = -40C to +85C, VDD = 2.0V VDD 3.6V, VSS = 0V.
500
+125oC
RSSI Current (A)
400 300 200 100 0 0 1 2
+85oC
T DR (s)
+25oC
-40oC
100 90 80 70 60 50 40 30 20 10 0 85C 25C -20C Temperature (C)
8%
14%
33% 60%
3
4
5
6
-40C
Input Voltage (V)
FIGURE 2-9: Typical RSSI Output Current vs. Input Signal Strength.
Note: There are slight variations between channels.
FIGURE 2-12: Example of Typical TDR Changes over Temperature. Input Signal Condition: Amplitude = 300 mVpp, Modulation Depth = 100%.
70 60
Capacitance (pF)
60 50
Ch. X Ch. Y Ch. Z
50 40 30 20 10 0 0 20 40 Bit Setting (steps) 60 80
TDF (s)
40 30 20 10 0 85C 25C -20C
60%
33% 14% 8% -40C
Temperature (C)
FIGURE 2-10: Typical Tuned Capacitance Value vs. Configuration Register Bit Setting (VDD = 3V,Temperature = -40C.
70 60
Capacitance (pF)
FIGURE 2-13: Example of Typical TDF Changes over Temperature. Input Signal Condition: Amplitude = 300 mVpp, Modulation Depth = 100%.
50 40 30 20 10 0 0 20 40 60 80 Bit Setting (Steps)
Ch. X Ch. Y Ch. Z
FIGURE 2-11: Typical Tuned Capacitance Value vs. Configuration Register Bit Setting (VDD = 3V,Temperature = +85C.
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MCP2030A
2.1 Performance Plots
(a) Sensitivity = 1.06 mVPP
Demodulated output
Input signal
(b) Sensitivity = 3 mVPP
Demodulated output
Input signal
FIGURE 2-14:
Input Sensitivity Example.
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MCP2030A
Note:
Ch2 is the input and Ch1 is the output (demodulated data appears after AGC Initialization time (TAGC). Output-Enable Filter is disabled.
FIGURE 2-15:
Typical AGC Initialization Time at Room Temperature (VDD = 3V).
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MCP2030A
Note:
Ch3 is the input with correct Output-Enable Filter timing. Ch1 is the demodulated LFDATA output. Ch2 is the ALERT pin output. It shows that the ALERT output pin maintains logic high if the input signal meets the programmed filter timing requirement.
FIGURE 2-16:
ALERT Output Example: With No Parity Error and no 32 ms Alarm Timer Time-out.
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MCP2030A
Note:
The 32 ms Alarm Timer is enabled only if the Output-Enable Filter is enabled. Ch3 is the input signal with incorrect Output-Enable Filter timing. Ch1 is the demodulated LFDATA output. No output since the input filter is not matched. Ch2 is the ALERT output. The output shows that the logic level changes after 32 ms from the AGC initialization time (TAGC) if the input signal does not meet the programmed filter timing requirement.
FIGURE 2-17:
ALERT Output Example: With 32 ms Alarm Timer Timed-out.
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MCP2030A
(a) Output (Ch 1): Device repeats Soft Reset after 16 ms inactivity timer has timed out
(b) Input (Ch 2): Input has no modulation
Note:
Ch 2 is the input without modulation (i.e., noise) Ch 1 is the output at the LFDATA pin due to the 16 ms Soft Inactivity Timer timed-out. Note the 3.5 ms AGC initialization time after the Soft Reset. The cases shown above apply when the Output Filter is disabled.
FIGURE 2-18: Examples of Soft Inactivity Timer Timed-out: This output is available only if the Output-Enable Filter is disabled.
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MCP2030A
Coil Voltage
LCX
Clock Pulses
SCLK
Clamp On Command
SDI
Coil Voltage
LCX
Clock Pulses
SCLK
Clamp Off Command
SDI
FIGURE 2-19:
Examples of Clamp-On and Clamp-Off Commands and Changes in Coil Voltage.
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MCP2030A
Demodulated output
Input signal with 77% modulation depth
FIGURE 2-20: Example of Minimum Modulation Depth Setting: Modulation Depth of Input Signal = 77%, Minimum Modulation Depth (MODMIN) Setting = 60%.
Demodulated output
Input signal with 56% modulation depth
Note:
There is no demodulated output since the modulation depth of the input signal is lower than the minimum modulation depth setting. The device will have demodulated output if the Minimum Modulation Depth option is set to 8%, 14%, or 33%.
FIGURE 2-21: Example of Minimum Modulation Depth Setting: Modulation Depth of Input Signal = 56%, Minimum Modulation Depth (MODMIN) Setting = 60%.
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MCP2030A
Demodulated output
Input signal with 42% modulation depth
FIGURE 2-22: Example of Minimum Modulation Depth Setting: Modulation Depth of Input Signal = 42%, Minimum Modulation Depth (MODMIN) Setting = 33%.
Demodulated output
Input signal with 14% modulation depth
FIGURE 2-23: Example of Minimum Modulation Depth Setting: Modulation Depth of Input Signal = 14%, Minimum Modulation Depth (MODMIN) Setting = 14%.
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MCP2030A
Filter 1
Output-Enable Filter Timing of Input Signal TOEH = 1 ms TOEL = 1 ms TOET = 3 ms Configuration Bit Settings OEH OEL
01
or
00 01
01
Filter 2
Output-Enable Filter Timing of Input Signal TOEH = 1 ms TOEL = 2 ms TOET = 4 ms Configuration Bit Settings OEH OEL
01
10
Filter 3
Output-Enable Filter Timing of Input Signal TOEH = 1 ms TOEL = 4 ms TOET = 6 ms Configuration Bit Settings OEH OEL
01
11
FIGURE 2-24: Outputs.
DS22235B-page 22
Examples of Output-Enable Filters 1 through 3 (Wake-up Filters) and Demodulated
2011 Microchip Technology Inc.
MCP2030A
Filter 4
Output-Enable Filter Timing of Input Signal TOEH = 2 ms TOEL = 1 ms TOET = 4 ms Configuration Bit Settings OEH OEL
10
or
00 01
10
Filter 5
Output-Enable Filter Timing of Input Signal TOEH = 2 ms TOEL = 2 ms TOET = 5 ms Configuration Bit Settings OEH OEL
10
10
Filter 6
Output-Enable Filter Timing of Input Signal TOEH = 2 ms TOEL = 4 ms TOET = 8 ms Configuration Bit Settings OEH OEL
10
11
FIGURE 2-25: Outputs.
Examples of Output-Enable Filters 4 through 6 (Wake-up Filters) and Demodulated
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MCP2030A
Filter 7
Output-Enable Filter Timing of Input Signal TOEH = 4 ms TOEL = 1 ms TOET = 6 ms Configuration Bit Settings OEH OEL
11
or
00 01
11
Filter 8
Output-Enable Filter Timing of Input Signal TOEH = 4 ms TOEL = 2 ms TOET = 8 ms Configuration Bit Settings OEH OEL
11
10
Filter 9
Output-Enable Filter Timing of Input Signal TOEH = 4 ms TOEL = 4 ms TOET = 10 ms Configuration Bit Settings OEH OEL
11
11
FIGURE 2-26: Outputs.
DS22235B-page 24
Examples of Output-Enable Filters 7 through 9 (Wake-up Filters) and Demodulated
2011 Microchip Technology Inc.
MCP2030A
LFDATA Output
Input Signal
Note:
Demodulated output is available immediately after AGC initialization.
FIGURE 2-27:
Input Signal and Demodulated Output When the Output-Enable Filter is Disabled.
LFDATA Output
Input Signal
Note:
Demodulated output is available only if the incoming signal meets the enable filter timing criteria that is defined in the Configuration Register 0 (Register 5-1). If the criteria is met, the output is available after the low timing (TOEL) of the Enable Filter.
FIGURE 2-28: Input Signal and Demodulator Output When Output-Enable Filter is Enabled and Input Meets Filter Timing Requirements.
2011 Microchip Technology Inc. DS22235B-page 25
MCP2030A
No LFDATA Output
Input Signal
FIGURE 2-29: No Demodulator Output When Output-Enable Filter is Enabled But Input Does Not Meet Filter Timing Requirements.
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2011 Microchip Technology Inc.
MCP2030A
Carrier Clock Output
Carrier Input
(a) Carrier Clock Output with Carrier/1 Option
Carrier Clock Output
Carrier Input
(b) Carrier Clock Output with Carrier/4 Option
FIGURE 2-30:
Carrier Clock Output Examples.
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DS22235B-page 27
MCP2030A
NOTES:
DS22235B-page 28
2011 Microchip Technology Inc.
MCP2030A
3.0 PIN DESCRIPTIONS
PIN FUNCTION TABLE
Symbol VSS CS SCLK/ALERT I/O/P P I I/O Ground Pin. Chip Select Digital Input Pin. Clock input for the modified 3-wire SPI interface. ALERT output: This pin goes low if there is a parity error in the configuration register or the 32 ms alarm timer is timed-out. Received Signal Strength Indicator (RSSI) current output. No Connect. Demodulated data output. Carrier clock output. Serial input or output data for the modified 3-wire SPI interface. Positive Supply Voltage Pin. Positive Supply Voltage Pin. Input pin for external LC antennas. Input pin for external LC antennas. Input pin for external LC antennas. No Connect. Common reference input for the external LC antennas. Ground Pin. Function The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
Pin No. 1 2 3
4 5 6
RSSI NC LFDATA/CCLK/SDIO
O N/A I/O
7 8 9 10 11 12 13 14
VDD VDD LCZ LCY LCX NC LCCOM VSS
P P I I I N/A I P
Legend: Type Identification: I = Input; O = Output; P = Power
3.1
Supply Voltage (VDD, VSS)
3.3
SPI Clock Input (SCLK/ALERT)
The VDD pin is the power supply pin for the analog and digital circuitry within the MCP2030A. This pin requires an appropriate bypass capacitor of 0.1 F. The voltage on this pin should be maintained in the 2.0V to 3.6V range for specified operation. The VSS pin is the ground pin and the current return path for both analog and digital circuitry of the MCP2030A. If an analog ground plane is available, it is recommended that this device be tie d to the an alog ground plane of the printed circuit board (PCB).
This pin becomes the SPI clock input (SCLK) when CS is low, and becomes the ALERT output when CS is high. The ALERT pin is an ope n-collector output. This pin has an internal pull-up resistor to ensure that no spurious SPI communication occurs between power-up and pin configuration of the MCU.
3.4
Received Signal Strength Indicator (RSSI)
3.2
Chip Select (CS)
The CS pin needs to stay high when the device is receiving input signals. Leaving the CS pin low will place the device in the SPI programming mode. The CS pin is an open collector output. This pin has an internal pull-up resistor to ensure that no spurious SPI communication occurs between power-up and pin configuration of the MCU.
This pin becomes the Received Signal Strength Indicator (RSSI) output current sink when the RSSI output option is selected.
2011 Microchip Technology Inc.
DS22235B-page 29
MCP2030A
3.5 Demodulated Data Output (LFDATA) Carrier Clock Output (CCLK) SPI Data I/O (SDIO) 3.6 LC Input (LCX, LCY, LCZ)
These pins are the input pins for the external LC resonant antenna circuits. The antenna circuits are connected between the LC pin and the LCCOM pin.
When the CS pin is high, this pin is an output pin for demodulated data or carrier clock, depending on output type selection. When carrier clock output (CCLK) is selected, the LFDATA output is a square pulse of the input carrier clock and is available as soon as the AGC stabilization time (TSTAB) is completed. When the CS pin is low, this pin becomes the SPI data input and output (SDIO).
3.7
LC Common Reference (LCCOM)
This pin is the common reference input pin for th e external LC resonant circuit.
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2011 Microchip Technology Inc.
MCP2030A
4.0 APPLICATION INFORMATION
4.1
The MCP2030A is a st and-alone 3-channel analog front-end device for lo w frequency (LF) se nsing and bidirectional transponder applications. By connecting three orthogonally-placed LC resonant antennas to the LC input pins, it can detect signals from all directions (x, y, and z). The device draws more current when all channels are enabled as compared to a single channel; therefore, it is recommended to disable any unused channels by setting Configuration Register 0 (Register 5-1). The device's high input sensitivity (as low as 1 mVPP) and ability to detect weakly modulated input signals (as low as 8%) with its low power feature set, makes the device suitable for various applications such as a low-cost hands-free Passive Keyless Entry (PKE) transponder, an LF Initiator sensor for Tire Pressure Monitoring Systems (TPMS) and long-range access control applications in the automotive and security industries.
Battery Back-up and Batteryless Operation
The device supports both battery back-up and batteryless operation by the addition of external components, allowing the device to be partially or completely powered from the field. Figure 4-1 shows an example of the external circuit for the battery back-up. Note: Voltage on LCCOM combined with coil input voltage must not exceed the maximum LC input voltage.
VBAT DBLOCK DLIM
VDD DFLAT1 CPOOL LX Air Coil
RLIM
LCX LCY LCZ
CX LY CY LZ
CZ LCCOM
DFLAT2
RCOM
CCOM
Legend: CCOM CPOOL DBLOCK DFLAT DLIM RCOM RLIM = = = = = = = LCCOM charging capacitor. Pool capacitor (or battery back-up capacitor), charges in field and powers device. Battery protection from reverse charge. Schottky for low forward bias drop. Field rectifier diodes. Voltage limiting diode, may be required to limit VDD voltage when in strong fields. LCCOM discharge path. Current limiting resistor, required for air coil in strong fields.
FIGURE 4-1:
External Circuit Example for LF Field Powering and Battery Backup Mode.
2011 Microchip Technology Inc.
DS22235B-page 31
MCP2030A
4.2 Application Examples
Figure 4-2 shows an example of an external circuit for a bidirectional communication transponder application. Each LC input pin is connected to an external LC resonant circuit. To achieve the best performance, the resonant frequency of the LC circuit needs to be matched to the d etecting carrier frequency of in terest. The resonant frequency is given by Equation 4-1: The output of the MCP2030A is fed into the external MCU. The external MCU can send data by clamping on and clamping off the MCP2030A coil voltages using an SPI command, or via a UHF transmitter. The RSSI output of the MCP2030A can be digitized by the MCU firmware. Users can also consider using a MCU that has an internal analog-to-digital converter (ADC) such as the PIC16F684 or a stand-alone ADC device. Figure 4-3 shows an example of a hands-free Passive Keyless Entry (PKE) s ystem. The base station unit transmits an LF command. The MCP2030A detects the base station command and feeds the detected output to the external MCU (PIC16F636). If the command is correct, the MCU responds via an external UHF transmitter or by using the LF talk-back modulators of the MCP2030A device. Figure 4-4 shows an example of the device being used for a tire pressure monitoring sensor application. The device detects the LF Initiator commands and transmits the tire pressure data to the base station via an external UHF transmitter.
EQUATION 4-1:
f o = -----------------1 2 LC
In typical 125 kHz applications, the L value is a few mH, and the C value is a few hundred pF, for example, L = 4.9 mH, and C = 331 pF. The resonant frequency can be fine-tuned by programming the internal tuning capacitors.
MCP2030A
SW1 SW2 SW3 SW4 VSS CS SCLK/ALERT VSS LCCOM NC LCX LCY C L air-core coil C ferrite-core coil L C L
PIC16F636/684
To ADC RSSI NC
LFDATA/CCLK/SDIO LCZ +3V VDD VDD +3V ferrite-core coil
315/434 MHz
RF Circuitry (UHF TX)
FIGURE 4-2: Applications.
Example of External Circuits for Bidirectional Communication Transponder
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2011 Microchip Technology Inc.
MCP2030A
ted Encryp Codes se Respon (UHF)
LED UHF Transmitter
LED UHF Receiver Microcontroller (MCU)
MCP2030A (3D Stand-Alone Analog Front-End) MCU
Ant. Y LF Transmitter/ Receiver
Response (125 kHz)
Ant. Z
Base Station
PKE Transponder
FIGURE 4-3:
Example of Bidirectional Hands-free Passive Keyless Entry (PKE) System.
RF Receiver
UH tire F respo pres nse sure with data
RF Transmitter MCU Tire Pressure Sensor MCP2030A
Initiator 125 kHz and mm co
LF Initiator
Note 1: The LF initiator sends LF commands to request the tire pressure data. 2: The MCP2030A picks up the LF commands and the MCU transmits the tire pressure data via an external UHF transmitter.
FIGURE 4-4:
Example of Tire Pressure Monitoring Sensor Applications.
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DS22235B-page 33
MCU (PIC16F636)
mand LF Com Hz) k (125
Ant. X
MCP2030A
NOTES:
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2011 Microchip Technology Inc.
MCP2030A
5.0 FUNCTIONAL DESCRIPTION AND THEORY OF DEVICE OPERATION
The modulation data comes from the external microcontroller section via the d igital SPI as "C lamp On", "Clamp Off" commands. Only those inputs that are enabled will execute the c lamp command. A ba sic block diagram of the modulation circuit is shown in Figure 5-1 and Figure 5-2. The modulation FET is also shorted momentarily after Soft Reset and Inactivity Timer time-out.
The MCP2030A contains three analog-input channels for signal detection and LF talk-back. This section provides the function description of the device. Each analog input channel has internal tuning capacitors, sensitivity control circuits, an input signal strength limiter and an LF talk-back modulation transistor. An Automatic Gain Control (AGC) loop is used for all three input channel gains. The output of e ach channel is ORed and fed into a demodulator. The digital output is passed to the LFDATA pin. Figure 5-1 shows the block diagram of the device and Figure 5-2 shows the input signal path. There are a total of eight Configuration registers. Six of them are used for device operation options, one for column parity bits and one for status indication of device operation. Each register has nine bits, including one row parity bit. These registers are readable and writable by SPI commands; except for the STATUS register, which is read-only. The device's features are dynamically controllable by programming the Configuration registers.
5.3
Tuning Capacitor
Each channel has internal tuning capacitors for external antenna tuning. The capacitor values are programmed by the Configuration registers up to 63 pF, 1 pF per step. Note: The user can control the tuning capacitor by programming the Configuration registers. See Register 5-2 through Register 5-4 for details.
5.4
Variable Attenuator
The variable attenuator is used to attenuate, via AGC control, the input signal voltage to avoid saturating the amplifiers and demodulators. Note: The variable attenuator function is accomplished by the device itself. The user cannot control its function.
5.1
RF Limiter 5.5
The RF Limiter limits LC pin input voltage by de-Q-ing the external LC resonant antenna circuit. The limiter begins de-Q-ing the external LC antenna when the input voltage exceeds VDE_Q, progressively de-Q-ing harder to reduce the antenna input voltage. The signal levels from all 3 channels are combined such that the limiter attenuates all 3 channels uniformly, in respect to the channel with the strongest signal.
Sensitivity Control
The sensitivity of each channel can be reduced by the channel's Configuration register sensitivity setting. This is used to desensitize the channel from optimum. Note: The user can desensitize the channel sensitivity by programming the Configuration registers. See Register 5-5 and Register 5-6 for details.
5.2
Modulation Circuit 5.6
The modulation circuit consists of a modulation transistor (FET), internal tuning capacitors and external LC antenna components. The modulation transistor and the internal tuning capacitors are connected between the LC input pin and LCCOM pin. Each LC input has its own modulation transistor. When the modulation transistor turns on, its low turn-on resistance (modulation resistance or RM) clamps the induced LC antenna voltage. The coil voltage is minimized when the modulation transistor turns on and maximized when the modulation transistor turns off. The modulation transistor's low RM results in a h igh modulation depth. The LF talk-back is achieved by turning on and off the modulation transistor.
AGC Control
The AGC controls the variable attenuator to lim it the internal signal voltage to av oid saturation of internal amplifiers and demodulators (Refer to Section 5.4 "Variable Attenuator"). The signal levels from all 3 channels are combined such that the AGC attenuates all 3 channels uniformly in respect to the channel with the strongest signal. Note: The AGC control function is accomplished by the device itself. The user cannot control its function.
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DS22235B-page 35
MCP2030A
5.7 Fixed Gain Amplifiers 1 and 2 5.12 Output-Enable Filter
FGA1 and FGA2 provide a maximum two-stage gain of 40 dB. Note: The user cannot control the gain of these two amplifiers. The output-enable filter enables the LFDATA output once the incoming signal meets the wake-up sequence requirements (see Section 5.15 "Configurable Output-Enable Filter").
5.8
Auto-Channel Selection
5.13
Received Signal Strength Indicator (RSSI)
The auto-channel selection feature is enabled if the Auto-Channel Select bit AUTOCHSEL<8> in Configuration Register 5 (Register 5-6) is set, and disabled if the bit is cleared. When this feature is active (i.e., AUTOCHSE <8> = 1), the control circuit checks the demodulator output of each input channel immediately after the AGC settling time (TSTAB). If the output is high, it allows this channel to p ass data, otherwise it i s blocked. The status of this operation is monitored by Status Register 7 bits <8:6> (Register 5-8). These bits indicate the current status of th e channel selection activity, and automatically updates for every Soft Reset period. The auto-channel selection function resets after each Soft Reset (or after Inactivity Timer time-out). Therefore, the blocked channels are re-enabled after Soft Reset. This feature can make the output signal cleaner by blocking any channel that was not high at the en d of TAGC. This function works only for demodulated data output, and is not a pplied for c arrier clock or R SSI output.
The RSSI provides a current which is proportional to the input signal amplitude (see Section 5.30.3 "Received Signal Strength Indicator (RSSI) Output").
5.14
Analog Front-End Timers
The device has an internal 32 kHz RC oscillator. The oscillator is used in several timers: * * * * * Inactivity Timer Alarm Timer Pulse Width Timer Period Timer AGC Settling Timer
5.14.1 5.14.2
RC OSCILLATOR INACTIVITY TIMER
The RC oscillator generates a 32 kHz internal clock.
5.9
Carrier Clock Detector
The Carrier Clock Detector senses the input carrier cycles. The output of the detector switches digitally at the signal carrier frequency. Carrier clock output is available when the output is selected by the DATOUT bit in Configuration Register 1 (Register 5-2).
The Inactivity Timer is used to automatically return the device to Standby mode, if there is no input signal. The time-out period is approximately 16 ms (TINACT), based on the 32 kHz internal clock. The purpose of the Inactivity Timer is to minimize current draw by automatically returning to the lower current Standby mode if, for the TINACT period, there is not an input signal. The timer is reset when: * An amplitude change occurs in LF input signal, either from high-to-low or low-to-high * the CS pin is low (any SPI command) * a timer-related Soft Reset occurs The timer starts after the AGC initialization period of time (TAGC). The timer causes a Sof t Reset when, for the TINACT period, a pre viously-received input signal does not change from either high-to-low or low-to-high. The Soft Reset returns the device to Standby mode, where most of the analog circuits, such as the AGC, demodulator, and RC oscillator, are powered down. This returns the device to the lower Standby Current mode.
5.10
Demodulator
The Demodulator consists of a full-wave rectifier, lowpass filter, peak detector and Data Slicer that detects the envelope of the input signal.
5.11
Data Slicer
The Data Slicer consists of a reference generator and comparator. The Data Slicer compares the input with the reference voltage. The re ference voltage comes from the minimum modulation depth requirement setting and input peak voltage. The data from all 3 channels are ORed together and sent to the output-enable filter.
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MCP2030A
5.14.3 ALARM TIMER 5.14.4 PULSE WIDTH TIMER
The Alarm Timer is used to notify the external MCU that the device is rec eiving an in put signal that does not pass the output-enable filter requirement. The time-out period is approximately 32 ms (TALARM) in the presence of continuing noise. The Alarm Timer time-out occurs if there is an input signal for longer than 32 ms that does not meet the output-enable filter requirements. The Alarm Timer time-out causes: a) b) the ALERT pin to go low the ALARM bit to set in th e Status Register 7 (Register 5-8) The Pulse Width Timer is used to ve rify that the received output enable sequence meets both the minimum TOEH and minimum TOEL requirements.
5.14.5
PERIOD TIMER
The Period Timer is used to verify that the received output enable sequence meets the maximum TOET requirement.
5.14.6
AGC INITIALIZATION TIMER (TAGC)
The external MCU is i nformed of the Alarm Timer time-out by monitoring the ALERT pin. If the Alarm Timer time-out occurs, the external MCU can take appropriate actions, such as lowering channel sensitivity or disabling channels. If the noise source is ignored, the device can return to a lower Standby Current Draw state. The timer is reset when the: * the CS pin is low (any SPI command) * the output-enable filter is disabled * the LFDATA pin is enabled (signal passed output-enable filter) The timer starts after the TAGC period. The timer causes a low output on the ALERT pin when the output-enable filter is enabled and modulated input signal is present for TALARM, but does not pass the output-enable filter requirement. Note: The Alarm timer is disabled if the output-enable filter is disabled.
This timer is used to keep the output-enable filter in Reset while the AGC settles on the input signal. The time-out period is approximately 3.5 ms. At end of this time (TAGC), the input should remain high (TPAGC), otherwise the counting is aborted and a Soft Reset is issued. See Figure 5-4 for details. Note 1: The device needs continuous and uninterrupted high input signal during AGC initialization time (TAGC). Any absence of signal during this time may reset the timer and a new input signal is needed for AGC settling time, or may result in improper AGC gain settings which will produce invalid output. 2: The rest of the device section wakes up if any of these input channels receive the AGC settling time correctly. Status Register 7 bits <4:2> (Register 5-8) indicate which input channels woke the device first. Valid input signal on multiple input pins can cause the indicator bit to be set on more than one channel.
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DS22235B-page 37
MCP2030A
LCX Tune X Mod
AGC Detector RF Lim Sensitivity Control X
/ 64 WAKEX
A
/ 64 LCCOM LCY Tune Y Mod AGC Detector Sensitivity Control Y A S WAKEZ WAKEY
RF Lim
LCCOM / 64 Detector Sensitivity Control Z A Watchdog
LCZ Tune Z Mod
AGC
RF Lim
Modulation Depth LCCOM To Sensitivity X To Sensitivity Y To Sensitivity Z AGC Preserve To Modulation Transistors To Tuning Cap X To Tuning Cap Y To Tuning Cap Z 32 kHZ Oscillator AGC Timer
B Output Enable Filter
Command Decoder/Controller
Configuration Registers
VSST
VDDT
RSSI
SCLK/ALERT
CS
LFDATA/ CCLK/SDIO
External MCU
FIGURE 5-1:
Functional Block Diagram.
DS22235B-page 38
2011 Microchip Technology Inc.
FIGURE 5-2:
AGC FGA1 Capacitor Tuning Carrier Detector + - / 64 Sens. Control Var Atten FGA2 LFDATA Output Enable Filter 00 /1 OR /4 CLKDIV
C
LCX/ LCY/ LCZ
RF Limiter
MOD FET
2011 Microchip Technology Inc.
01 10 RSSI GEN 11 DETX DETY DETZ
A
> 4 VPP
Input Signal Path.
WAKEX WAKEY WAKEZ 32 kHz Clock/AGC Timer
C
LFDATA
DATOUT
LCCOM
RSSI
0.1V
-
1
0
AGCSIG
0.4V
Decode X Y Z REF GEN Demodulator - + AUTOCHSEL
Configuration
Registers
A
Full-Wave Rectifier
Low-Pass Filter
Peak Detector
AGC Feedback Amplifier
+
AGCACT
Legend:
MOD Depth Control Data Slicer Auto-Channel Selector
FGA = Fixed Gain Amplifier
CHX CHY CHZ
ACT
FWR = Full-wave Rectifier
LPF = Low-pass Filter
MCP2030A
DS22235B-page 39
PD = Peak Detector
X Y Z
B
MCP2030A
5.15 Configurable Output-Enable Filter
The purpose of this filter is to enable the LFDATA output and wake the external microcontroller only after receiving a specific sequence of pulses on the LC input pins. Therefore, it prevents waking up the ext ernal microcontroller due to noise or unwanted input signals. The circuit compares the timing of the demodulated header waveform with a pre-defined value, and enables the demodulated LFDATA output when a match occurs. The output-enable filter consists of a high (TOEH) and low (TOEL) duration of a pul se immediately after the AGC settling gap time. The selection of high and low times further implies a m ax period of tim e. The output-enable high and low times are determined by SPI programming. Figure 5-3 and Figure 5-4 show the output-enable filter waveforms. There should be no missing cycles during TOEH. Missing cycles may result in failing the output-enable condition.
Required Output Enable Sequence TSTAB (TAGC + TPAGC) TGAP t TOEH Device Wake-up and AGC Stabilization AGC Gap Pulse t TOET t TOEL LFDATA output is enabled on this rising edge Start bit Data Packet
Demodulator Output
FIGURE 5-3:
Output-Enable Filter Timing.
DS22235B-page 40
2011 Microchip Technology Inc.
MCP2030A
Start bit for data
Demodulated LFDATA Output
3.5 ms
LF Coil Input
TPAGC TGAP Low Current (need Gap TAGC Standby "high") Pulse Mode (AGC initialization time) TSTAB (AFE Stabilization) Filter starts
t TOEL t TOEH t TOET
t 2 TE
Filter is passed and LFDATA is enabled
Legend:
TAGC TPAGC TSTAB TE TGAP TOEH TOEL
= = = = = = = =
AGC initialization time High time after TAGC AGC stabilization time (TAGC + TPAGC) Time element of pulse (minimum pulse width) AGC stabilization gap Minimum output-enable filter high time Minimum output-enable filter low time Maximum output-enable filter period
TOET
FIGURE 5-4:
Output-Enable Filter Timing Example (Detailed).
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DS22235B-page 41
MCP2030A
TABLE 5-1:
OEH <1:0> 01 01 01 01 10 10 10 10 11 11 11 11 00 Note 1:
OUTPUT-ENABLE FILTER TIMING
OEL <1:0> 00 01 10 11 00 01 10 11 00 01 10 11
XX
TOEH (ms) 1 1 1 1 2 2 2 2 4 4 4 4
TOEL (ms) 1 1 2 4 1 1 2 4 1 1 2 4 Filter Disabled
TOET (ms) 3 3 4 6 4 4 5 8 6 6 8 10
If the filter resets due to a long high-time (TOEH > TOET), the high-pulse timer will not begin timing again until after a gap of TE and another low-to-high transition occurs on the demodulator output. Disabling the output-enable filter disables the TOEH and TOEL requirement, and the device passes all detected data. See Figure 2-28, Figure 2-29 and Figure 2-30 for examples. When viewed from an application perspective - from the pin input - the actual output-enable filter timing must factor in the analog delays in the input path (such as demodulator charge and discharge times). * TOEH - TDR + TDF * TOEL + TDR - TDF The output-enable filter starts immediately after TGAP, the gap after AGC stabilization period.
5.16
Input Sensitivity Control
The timing values of TOEH and TOEL are minimum and TOET is maximum at room temperature and VDD = 3.0V, 32 kHz oscillator.
TOEH is measured from the rising edge of the demodulator output to the first falling edge. The pulse width must fall within TOEH t TOET. TOEL is measured from the falling edge of the demodulator output to the rising edge of the next pulse. The pulse width must fall within TOEL t TOET. TOET is measured from rising edge to the next rising edge (i.e., the sum of TOEH and TOEL). The sum of TOEH and TOEL must be t TOET. If the Configuration Register 0 (Register 5-1), OEH<8:7> is set to `00', then the filter is disabled. See Figure 2-28 for this case. The filter will reset, requiring a complete new successive high and low period to enable LFDATA, under the following conditions: * the received high is not greater than the configured minimum TOEH value * during TOEH, a loss of signal for longer than 56 s causes a filter reset * the received low is not greater than the configured minimum TOEL value * the received sequence exceeds the maximum TOET value: - TOEH + TOEL > TOET - or TOEH > TOET - or TOEL > TOET * a Soft Reset SPI command is received
The device has typical input sensitivity of 1 mVPP. This means any input signal with amplitude greater than 1 mVPP can be detected. The internal AGC loop regulates the detecting signal amplitude when the input level is greater than approximately 20 mVPP. This signal amplitude is called "AGC-active level". The AGC loop regulates the input voltage so that the input signal amplitude range will be kept within the linear range of the detection circuits without saturation. The AGC Active Status bit (AGCACT<5>) in Status Register 7 (Register 5-8) is set if the AGC loop regulates the input voltage. Table 5-2 shows the input sensitivity comparison when the AGCSIG option is used. When AGCSIG option bit is set, the demodulated output is available only when the AGC loop is active (see Table 5-1). The channel input sensitivity can be reduced by setting the appropriate configuration registers. Configuration Register 3 (Register 5-4), Configuration Register 4 (Register 5-5), and Configuration Register 5 (Register 5-6) have the option to reduce each channel gain from 0 dB to approximately -30 dB.
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MCP2030A
TABLE 5-2: INPUT SENSITIVITY VS. MODULATED SIGNAL STRENGTH SETTING (AGCSIG <7>)
Description Option Disabled - Detect any input signal level (demodulated data and carrier clock). Option Enabled - No output until AGC Status = 1 (i.e., VPEAK 20 mVPP) (demodulated data and carrier clock). * Provides the best signal to noise ratio. Input Sensitivity (Typical) 1.0 mVPP 20 mVPP AGCSIG<7> (Config. Register 5) 0 1
5.17
Input Channels (Enable/Disable)
5.19
AGC Preserve
Each channel can be individually enabled or disabled by programming bits in Configuration Register 0<3:1> (Register 5-1). The purpose of having an option to disable a particular channel is to minimize current draw by powering down as much circuitry as possible, if th e channel is not needed for operation. The exact circuits disabled when an input is disabled are amplifiers, detector, full-wave rectifier, data slicer, and modulation FET. However, the RF input limiter remains active to protect the silicon from excessive antenna input voltages.
5.18
AGC Amplifier
The circuit automatically amplifies input signal voltage levels to an acceptable level for the da ta slicer. Fast attack and slow release by nature, the AGC tracks the carrier signal level and not the modulated data bits. The AGC inherently tracks the strongest of the three antenna input signals. The AGC requires an AGC initialization time (TAGC). The AGC will attempt to regulate a channel's peak signal voltage into the data slicer to a desired regulated AGC voltage - reducing the input path's gain as the signal level attempts to increase above regulated AGC voltage, and allowing full amplification on signal levels below the regulated AGC voltage. The AGC has two modes of operation: 1. During the AGC initialization time (TAGC), the AGC time constant is fast, allowing a reasonably short acquisition time of the continuous input signal. After TAGC, the AGC switches to a slower time constant for data slicing.
The AGC preserve feature is used to preserve the AGC value during the AGC initialization time (TAGC) and apply the value to the data slicing circuit for the following data streams instead of using a new tracking value. This feature is useful to d emodulate the input signal correctly when the input has random amplitude variations at a given time period. This feature is enabled when the device receives an AGC Preserve On command and disabled if it receives an AGC Preserve Off command. Once the AGC Preserve On command is received, the device acquires a new AGC value during each AGC initialization time and preserves the value until a Soft Reset or an AGC Preserve Off command is issued. Therefore, it does not need to issue another AGC Preserve On command. An AGC Pre serve Off command is needed to disable the AGC preserve feature (see Section 5.31.2.5 "AGC Preserve On Command" and Section 5.31.2.6 "AGC Preserve Off Command" for AGC Preserve commands).
2.
Also, the AGC is frozen when the input signal envelope is low. The AGC tracks only high envelope levels.
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DS22235B-page 43
MCP2030A
5.20
a) b) c) d)
Soft Reset
5.21
The Soft Reset is issued in the following events: After Power-on Reset (POR), After Inactivity timer time-out, If an "Abort" occurs, After receiving SPI Soft Reset command.
Minimum Modulation Depth Requirement for Input Signal
The "Abort" occurs if th ere is no po sitive signal detected at th e end of th e AGC initialization period (TAGC). The Soft Reset initializes internal circuits and brings the device into a l ow current Standby mode operation. The internal circuits that are initialized by the Soft Reset include: * * * * Output-Enable Filter AGC circuits Demodulator 32 kHz Internal Oscillator
The device demodulates the modulated input signal if the modulation depth of the input signal is greater than the minimum requirement that is programmed in Configuration Register 5 (Register 5-6). Figure 5-5 shows the definition of the modulation depth and examples. MODMIN<6:5> of th e Configuration Register 5 offer four options: 60%, 33%, 14% and 6%. The default setting is 33%. The purpose of this feature is to enhance the demodulation integrity of the input signal. The 6% setting is the best choice for the input signal with weak modulation depth, which is typically observed near the high-voltage base station antenna and also at far-distance from the base station antenna. It gives the best demodulation sensitivity, but is very susceptible to noise spikes that can result in a bit detection error. The 60% setting can reduce the bit errors caused by noise, but gives the least demodulation sensitivity. See Table 5-3 for minimum modulation depth requirement settings.
The Soft Reset has no effect on the Configuration register setup, except for some of t he AFE Status Register 7 bits. (Register 5-8). The circuit initialization takes one internal clock cycle (1/32 kHz = 31 .25 s). During the initialization, the modulation transistors between each input and LCCOM pins are turned-on to discharge any internal/external parasitic charges. The modulation transistors are turn ed-off immediately after the initialization time. The Soft Reset is executed in Active mode only. It is not valid in Standby mode.
TABLE 5-3:
SETTING FOR MINIMUM MODULATION DEPTH REQUIREMENT
Modulation Depth 33% (default) 60% 14% 8%
MODMIN Bits (Config. Register 5) Bit 6 0 0 1 1 Bit 5 0 1 0 1
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MCP2030A
(a) Modulation Depth Definition Amplitude Modulation Depth (%) = Input Signal t B A A-B X 100% A+B
(b) Input signal vs. minimum modulation depth setting vs. LFDATA output Amplitude 7 mVPP 10 mVPP Coil Input Strength Modulation Depth (%) = Input Signal t 10 - 7 X 100% = 17.64% 10 + 7
Input signal with modulation depth = 17.64% Demodulated lfdata Output when MODMIN Setting = 14% t (LFDATA output = toggled) Amplitude Demodulated lfdata Output if MODMIN setting = 33% (LFDATA output = not toggled) t
0
FIGURE 5-5:
Modulation Depth Examples.
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5.22 Low-Current Sleep Mode
The device can stay at an ultra low-current mode (Sleep mode) when it receives a Sleep command via the SPI. All circuits including the RF Limiter (except the minimum circuitry required to retain register memory and SPI capability), will be powered down to minimize the current draw. POR or any SPI command, other than the Sleep command, is required to wake the device from Sleep. The Column Parity Register (Configuration Register 6) holds column parity bits; each bit is calculated over the respective columns (Configuration registers 0 to 5) of the Configuration bits. The Status register is not included for the column parity bit calculation. Parity is to be odd. The parity bit set or cleared makes an o dd number of set bits. The user needs to calculate the row and column parity bits using the contents of the registers and program them. During operation, the device continuously calculates the row and column parity bits of the configuration memory map. If a parity error occurs, the device lowers the SCLK/ALERT pin (interrupting the microcontroller section) indicating the configuration memory has been corrupted or unloaded and needs to be reprogrammed. At an initial condition after a Power-On-Reset, the values of the registers are all clear (default condition). Therefore, the device will issue the parity bit error by lowering the SCLK/ALERT pin. If the user reprograms the registers with the correct parity bits, the SCLK/ALERT pin will be to ggled to logic high level immediately. The parity bit errors do not change or a ffect any functional operation. Table 5-4 shows an example of the register values and corresponding parity bits.
5.23
Low-Current Standby Mode
The device is in Standby mode when no input signal is present on the input pins, but is powered and ready to receive any incoming signals.
5.24
Low-Current Active Mode
The device is in Low-Current Active mode when an input signal is present on any input pin and internal circuitry is switching with the received data.
5.25
Error Detection of Configuration Register Data
The Configuration registers are volatile memory. Therefore, the c ontents of th e registers can be c orrupted or cleared by any electrical incidence such as battery disconnect. To ensure data integrity, the device has an error detection mechanism using the row and column parity bits of the Configuration register memory map. Bit 0 of each register is a row parity bit that is calculated over the eight Configuration bits (from bit 1 to bit 8).
TABLE 5-4:
CONFIGURATION REGISTER PARITY BIT EXAMPLE
Bit 8 1 0 0 0 0 1 1 Bit 7 0 0 0 0 0 0 1 Bit 6 1 0 0 0 0 0 0 Bit 5 0 0 0 0 0 0 1 Bit 4 1 0 0 0 0 0 0 Bit 3 0 0 0 0 0 0 1 Bit 2 0 0 0 0 0 0 1 Bit 1 0 0 0 0 0 0 1 Bit 0 (Row Parity) 0 1 1 1 1 0 1
Register Name Configuration Register 0 Configuration Register 1 Configuration Register 2 Configuration Register 3 Configuration Register 4 Configuration Register 5 Configuration Register 6 (Column Parity Register)
5.26
Factory Calibration
5.27
De-Q-ing the Antenna Circuit
The device is calibrated during probe test to reduce the device-to-device variation in standby current, internal timing and sensitivity, as well as channel-to-channel sensitivity variation.
When the transponder is close to the base station, the transponder coil may develop coil voltage higher than VDE_Q. This condition is called "near field". The device detects the strong near field signal through the AGC control, and de-Q-ing the antenna circuit to reduce the input signal amplitude.
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MCP2030A
Input at LC input pins
Full-wave Rectifier output
Demodulated LFDATA output TDR TDF
FIGURE 5-6:
Demodulator Charge and Discharge. 5.30.1 DEMODULATOR OUTPUT
5.28
Demodulator
The demodulator recovers the modulation data from the received signal, containing carrier plus data, by appropriate envelope detection. The demodulator has a fast rise (charge) time (TDR) and a fall time (TDF) appropriate to an envelope of input signal (see Section 1.0 "Electrical Specifications" for TDR and TDF specifications). The demodulator contains the full-wave rectifier, low-pass filter, peak detector and data slicer.
The demodulator output is the default configuration of the output selection. This is the output of an envelope detection circuit. See Figure 5-6 for t he demodulator output. For a clean data output or to save operating power, the input channels can be individually enabled or disabled. If more than one channel is enabled, the output is the sum of each output of all enabled channels. There will be no v alid output if al l three channels are disabled. When the demodulated output is selected, the output is available in two different conditions depending on how the options of Configuration Register 0 (Register 5-1) are set: Output-Enable Filter is disabled or enabled. See Section 2.0 "Typical Performance Curves" for various demodulated data output. Related Configuration register bits: * Configuration Register 1 (Register 5-2), DATOUT <8:7>: - bit 8 bit 7 0 0 1 0 0: Demodulator Output 1: Carrier Clock Output 0: RSSI Output 1: RSSI Output
5.29
POR
This circuit remains in a Reset state until a sufficient supply voltage is applied. The Reset releases when the supply is sufficient for correct device operation, nominally VPOR. The Configuration registers are all cleared on a PO R. As the Configuration registers are protected by odd row and column parity, the ALERT pin will be pulled down - indicating to the external microcontroller section that the configuration memory is cleared and requires new programming.
5.30
LFDATA Output Selection
The LFDATA output can be configured to pass the Demodulator output, Received Signal Strength Indicator (RSSI) out put, or Carrier Clock (CCLK). See Configuration Register 1 (Register 5-2) for more details.
* Configuration Register 0 (Register 5-1): all bits
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MCP2030A
5.30.2 CARRIER CLOCK OUTPUT
When the carrier clock output is selected, the LFDATA output is a square pulse of the input carrier clock and available as soon as the AGC stabilization time (TAGC) is completed. There are two Configuration register options for the carrier clock output: (a) clock divide-by one or (b) clock divide-by four, depending on bit DATOUT<7> of C onfiguration Register 2 (Register 5-3). The carrier clock output is available immediately after the AGC settling time. The Output-Enable Filter, AGCSIG, and MODMIN options are applicable for the carrier clock output in the same way as the demodulated output. The input channel can be individually enabled or disabled for the output. If more than one channel is enabled, the output is the sum of each output of all enabled channels. Therefore, the carrier clock output waveform is not as precise as when only one channel is enabled. It is recommended to enable one channel only if a precise output waveform is desired. There will be no valid output if all three channels are disabled. See Figure 2-30 for carrier clock output examples. Related Configuration Register Bits: * Configuration Register 1 (Register 5-2), DATOUT <8:7>: bit 8 bit 7 0 0 1 1 0: Demodulator Output 1: Carrier Clock Output 0: RSSI Output 1: RSSI Output When the device receives an SPI command during the RSSI output, the RSSI mo de is temporary disabled until the SPI communication is completed. It returns to the RSSI mode again after the SPI communication is completed. The RSSI mode is held until another output type is selected (CS low turns off the RSSI signal). To obtain the RSSI output for a particular input channel, or to save operating power, the input channel can be individually enabled or disabled. If more than one channel is enabled, the RSSI output is from the strongest signal channel. There will be no valid output if all three channels are disabled. The RSSI output current is linearly proportional to the input signal strength. There are variations from channel to channel and device to device. The linearity (ILRRSSI) of the RSSI output current is tested by sampling the outputs for three input points: 37 mVPP, 100 mVPP, and 370 mVPP. The RSSI output current for 100 mVPP of input signal is compared with the expected output current obtained from the line that is connecting the two endpoints (37 mVPP and 370 mVPP). Equation 5-1 and Figure 5-7 show the details for the RSSI linearity specification.
EQUATION 5-1:
ILRRSSI(%) =
RSSI LINEARITY SPECIFICATION
Deviation at 100 mVPP of Input Signal IRSSI for 370 mVPP of Input Signal
x 100%
where, Deviation at 100 mVPP of Input Signal = [IRSSI measured - IRSSI expected] at 100 mVPP of input signal. IRSSI expected = RSSI current obtained from the line that is connecting two endpoints (RSSI output currents for 37 mVPP and 370 mVPP of inputs).
* Configuration Register 2 (Register 5-3), CLKDIV<7>: 0: Carrier Clock/1 1: Carrier Clock/4 * Configuration Register 0 (Register 5-1): all bits are affected * Configuration Register 5 (Register 5-6)
An analog current output is available at the RSSI pin when the Received Signal Strength Indicator (RSSI) output is selected by the Configuration register. The analog current is linearly proportional to the input signal strength. All timers in the circuit, such as inactivity timer, alarm timer, and AGC initialization time, are disabled during the RSSI mode. Therefore, the R SSI output is not affected by the AGC stabilization time, and available immediately when the RSSI option is selected. The device enters Active mode immediately when the RSSI output is selected.
RSSI Output Current [A]
5.30.3
RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) OUTPUT
y
y = a+bx
d
= Measured = Expected d = Deviation
37 mVPP
100 mVPP
370 mVPP
x
Input Signal Amplitude
FIGURE 5-7:
RSSI Linearity Test Example
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MCP2030A
Related Configuration Register Bits: * Configuration Register 1 (Register 5-2), DATOUT<8:7>: bit 8 0 0 1 1 bit 7 0: Demodulated Output 1: Carrier Clock Output 0: RSSI Output 1: RSSI Output
5.30.3.1
ANALOG-TO-DIGITAL DATA CONVERSION OF RSSI SIGNAL
* Configuration Register 2 (Register 5-3), RSSIFET<8>: 0: Pull-Down MOSFET off 1: Pull-Down MOSFET on. Note: The pull-down MOSFET option is valid only when the RSSI output is selected. The MOSFET is not controllable by users when demodulated or carrier clock output option is selected.
The RSSI output is an a nalog current. It needs an external analog-to-digital (ADC) data conversion device for digitized output. The ADC data conversion can be accomplished by using a stand-alone external ADC device, an external MCU that has internal ADC features, or an external MCU that has no ADC features but instead uses firmware. The RSSIFET is used to discharge any external charge on the LFDATA pin in the RSSI Output mode. The MOSFET can be turned on or off with bit RSSIFET<8> of C onfiguration Register 2 (Register 5-3). When it is turned on, the internal MOSFET provides a discharge path for the external capacitor that is connected at the LFDATA pin. This MOSFET option is valid only if RSSI output is selected and not controllable by users for demodulated or carrier clock output options. See separate application notes for various external ADC implementation methods for this device. See Figure 5-8 for RSSI output path.
* Configuration Register 0 (Register 5-1): all bits are affected.
RSSI Output Current Generator VDD Off if RSSI active Current Output
RSSI Pin LFDATA/CCLK Pin
RSSIFET(1)
RSSI Pull-down MOSFET (controlled by Config. 2, bit 8)
Note 1:
The RSSIFET is used to discharge any external capacitor that is connected at the LFDATA pin.
FIGURE 5-8:
RSSI Output Path.
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5.31
5.31.1 Configuration Registers SPI COMMUNICATION
The SPI communication is used to read from or write to the Configuration registers and to send command-only messages. Three pins are used for SPI SCLK/ALERT, and communication: CS, LFDATA/RSSI/CCLK/SDIO. Figure 5-9, Figure 5-10 and Figure 5-11 show examples of the SPI communication sequences. When these pins are connected to the external MCU I/O pins, the following are needed: CS * Pin is permanently an input with an internal pull-up SCLK/ALERT * Pin is an open collector output when CS is high. An internal pull-up resistor exists to ensure no spurious SPI communication between powering and the MCU configuring its pins. This pin becomes the SPI clock input when CS is low LFDATA/CCLK/SDIO * Pin is a digital output (LFDATA) so long as CS is high. During SPI communication, the pin is the SPI data input (SDI) unless performing a register Read, where it will be the SPI data output (SDO).
MCU pin is input.
CS pulled high by internal pull-up
CS
SCLK/ALERT
LFDATA/CCLK/SDIO
MCU pin is input.
FIGURE 5-9:
Power-Up Sequence.
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MCU pin is input. SCLK pulled high by internal pull-up
ALERT (open collector output)
LFDATA (output)
Driving CS high
MCU pin output
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MCP2030A
TCSH CS MCU pin to Input
2 6
TCSSC Driven low by MCU
4 16 Clocks for Write Command, Address and Data
TSCCS TCS1 Driven low by MCU
7
TCS0 Driven low by MCU
THI
TLO
SCLK/ALERT ALERT (output)
MSb SCLK (input) TSU MCU pin still Input MCU pin to Output
1/FSCLK
LSb
ALERT (output)
LFDATA/CCLK/SDIO LFDATA (output)
SDI (input)
3
MCU pin to Input
1
THD
5
LFDATA (output)
MCU SPI Write Details: 1. 2. 3. 4. 5. 6. 7. Drive the open collector ALERT output low - to ensure that no false clocks occur when CS drops. Drop CS - SCLK/ALERT becomes SCLK input, and LFDATA/CCLK/SDIO becomes SDI input. Change LFDATA/CCLK/SDIO connected pin to output - driving SPI data. Clock in 16-bit SPI Write sequence - command, address, data, and parity bit. Change LFDATA/CCLK/SDIO connected pin to input. Raise CS to complete the SPI Write. Change SCLK/ALERT back to input.
FIGURE 5-10:
SPI Write Sequence.
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CS
MCU pin to Input
4 16 Clocks for Read Command,
TCSSC Driven low by MCU
Address and Dummy Data THI TLO
TSCCS TCS1
TCS0 TCSSC Driven low by MCU
8 16 Clocks for Read Result
10
TCSSC TCS1 Driven low by MCU
MCU pin to Input
SCLK/ALERT ALERT (output)
1
MSb SCLK (input) TSU THD MCU pin still Input MCU pin to Output
1/FSCLK
LSb (output)
ALERT
SCLK (input)
ALERT (output)
MCU pin to Input
TDO
LFDATA/RSSI/CCLK/SDIO
LFDATA SDI (output) (input)
3
5
LFDATA (output)
SDO (output)
LFDATA (output)
MCU SPI Read Details: 1. 2. 3. 4. 5. 6. 7. 8. 9.
2011 Microchip Technology Inc.
Drive the open collector ALERT output low - to ensure that no false clocks occur when CS drops. Drop CS - SCLK/ALERT becomes SCLK input, and LFDATA/CCLK/SDIO becomes SDI input. Change LFDATA/CCLK/SDIO connected pin to output - driving SPI data. Clock in 16-bit SPI Read sequence - command, address, and dummy data. Change LFDATA/CCLK/SDIO connected pin to input. Raise CS to complete the SPI Read entry of command and address. Drop CS - AFE SCLK/ALERT becomes SCLK input, and LFDATA/CCLK/SDIO becomes SDO output. Clock out 16-bit SPI Read result - first seven bits clocked-out are dummy bits, the next eight bits are the Configuration register data, and the last bit is the Configuration register row parity bit. Raise CS to complete the SPI Read. The TCSH is considered as one clock. Therefore, the Configuration register data appears at 6th clock after TCSH.
10. Change SCLK/ALERT back to input. Note:
FIGURE 5-11:
SPI Read Sequence.
Driven low by MCU
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MCP2030A
TCSH
2 6 7 9
TCSH
TCS0
MCP2030A
5.31.2 COMMAND DECODER/CONTROLLER
The circuit executes 8 SPI commands from the external MCU. The command structure is: Command (3 bits) + Configuration Address (4 bits) + Data Byte and Row Parity Bit with the Most Significant bit first. Table 5-5 shows the available SPI commands. The device operates in SPI mode 0,0. In mode 0,0 the clock idles in the low state (Figure 5-12). SDI data is loaded into the device on the rising edge of SCLK, and SDO data is clocked out on the falling edge of SCLK. There must be multiples of 16 clocks (SCLK) while CS is low or commands will abort.
TABLE 5-5:
SPI COMMANDS
Data Row Parity X X X X X X P P P P P P P X P P P P P P P X Description
Command Address
Command only - Address and Data are "Don't Care", but need to be clocked in regardless. 000 001 010 011 100 101 110 XXXX XXXX XXXX XXXX XXXX XXXX 0000 0001 0010 0011 0100 0101 0110 0111 111 0000 0001 0010 0011 0100 0101 0110 0111 Note: XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX Config Byte 0 Config Byte 1 Config Byte 2 Config Byte 3 Config Byte 4 Config Byte 5 Column Parity Status Config Byte 0 Config Byte 1 Config Byte 2 Config Byte 3 Config Byte 4 Config Byte 5 Column Parity Not Used Clamp on - enable modulation circuit Clamp off - disable modulation circuit Enter Sleep mode (any other command wakes the AFE) AGC Preserve On - to temporarily preserve the current AGC level AGC Preserve Off - AGC again tracks strongest input signal Soft Reset - resets various circuit blocks General - options that may change during normal operation LCX antenna tuning and LFDATA output format LCY antenna tuning LCZ antenna tuning LCX and LCY sensitivity reduction LCZ sensitivity reduction and modulation depth Column parity byte for Config Byte 0 -> Config Byte 5 Status - parity error, which input is active, etc. Output-enable filter, channel enable/disable, etc. LCX antenna tuning and LFDATA output type LCY antenna tuning LCZ antenna tuning LCX and LCY sensitivity reduction LCZ sensitivity reduction and modulation depth Column parity byte for Config Byte 0 -> Config Byte 5 Register is readable, but not writable
Read Command - Data will be read from the specified register address.
Write Command - Data will be written to the specified register address.
`P' denotes the row parity bit (odd parity) for the respective data byte.
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MCP2030A
CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCLK
MSb SDIO bit 2 bit 0 bit 3 bit 0 bit 8 bit 1 Data Byte
LSb
Command
Address
Row Parity Bit
FIGURE 5-12: 5.31.2.1
Detailed SPI Timing (AFE). 5.31.2.5 AGC Preserve On Command
Clamp On Command
This command results in activating (turning on) the modulation transistors of all enabled channels; channels enabled in Configuration Register 0 (Register 5-1).
5.31.2.2
Clamp Off Command
The AGC Preserve On command results in preserving the AGC level during each AGC initialization time and applying the value to the data slicing circuit for the following data stream, instead of using a new tracking value . The preserved AGC value is reset by a Soft Reset, and a new AGC value is acquired and preserved when it starts a new AGC initialization time. This feature is disabled by an AG C Preserve Off command (see Section 5.19 "AGC Preserve").
This command results in deactivating (turning off) the modulation transistors of all channels.
5.31.2.3
Sleep Command
This command places the device in Sleep mode - minimizing current draw by disabling all but the essential circuitry. Any other command wakes the device from Sleep (e.g., Clamp Off command).
5.31.2.6
AGC Preserve Off Command
5.31.2.4
Soft Reset Command
The device issues a S oft Reset when it receives an external Soft Reset command. The external Soft Reset command is typically used to end an SPI communication sequence or to initialize the device for the next signal detection sequence, etc. See Section 5.20 "Soft Reset" for more details on Soft Reset. If a Soft Reset command is sent during a "Clamp-on" condition, the device still keeps the "Clamp-on" condition after the Soft Reset execution. The Soft Reset is executed in Active mode only, not in Standby mode. The SPI Soft Reset command is ignored if the device is not in Active mode.
This command disables the AGC preserve feature and returns to the normal AGC tracking mode, fast tracking during AGC settling time and slow tracking after that (see Section 5.19 "AGC Preserve").
5.31.3
READ/WRITE COMMANDS FOR CONFIGURATION REGISTERS
The device includes eight Configuration registers, including a Column Parity register and Status register. All registers are readable and writable via SPI, except the Status register, which is read-only. Bit 0 of each register is a row parity bit (except for Status Register 7) that makes the register contents an odd number.
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bit 0
MCP2030A
TABLE 5-6: CONFIGURATION REGISTERS SUMMARY
Bit 8 OEH DATOUT RSSIFET CLKDIV Unimplemented Channel X Sensitivity Control AGCSIG MODMIN MODMIN Column Parity Bits Active Channel Indicators AGCACT Wake-up Channel Indicators ALARM Bit 7 Bit 6 OEL Bit 5 Bit 4 ALRTIND Bit 3 LCZEN Bit 2 LCYEN Bit 1 LCXEN Bit 0 R0PAR R1PAR R2PAR R3PAR R4PAR R5PAR R6PAR PEI Register Name Configuration Register 0 Configuration Register 1 Configuration Register 2 Configuration Register 3 Configuration Register 4 Column Parity Register 6 Status Register 7
Channel X Tuning Capacitor Channel Y Tuning Capacitor Channel Z Tuning Capacitor Channel Y Sensitivity Control Channel Z Sensitivity Control
Configuration Register 5 AUTOCHSEL
REGISTER 5-1:
OEH1 bit 8 Legend:
CONFIGURATION REGISTER 0 (ADDRESS: 0000)
R/W-0 OEL1 R/W-0 OEL0 R/W-0 ALRTIND R/W-0 LCZEN R/W-0 LCYEN R/W-0 LCXEN R/W-0 R0PAR bit 0
R/W-0 OEH0
Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 8-7
OEH<1:0>: Output-Enable Filter High Time (TOEH) bit 00 = Output-Enable Filter disabled (no wake-up sequence required, passes all signal to LFDATA) 01 =1 ms 10 =2 ms 11 =4 ms OEL<1:0>: Output-Enable Filter Low Time (TOEL) bit 00 =1 ms 01 =1 ms 10 =2 ms 11 =4 ms ALRTIND: ALERT bit, output triggered by: 1 = Parity error and/or expired Alarm timer (receiving noise, see Section 5.14.3 "Alarm Timer") 0 = Parity error LCZEN: LCZ Enable bit 1 = Disabled 0 = Enabled LCYEN: LCY Enable bit 1 = Disabled 0 = Enabled LCXEN: LCX Enable bit 1 = Disabled 0 = Enabled R0PAR: Register 0 Parity bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
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MCP2030A
REGISTER 5-2:
R/W-0
DATOUT1
CONFIGURATION REGISTER 1 (ADDRESS: 0001)
R/W-0
LCXTUN5
R/W-0
DATOUT0
R/W-0
LCXTUN4
R/W-0
LCXTUN3
R/W-0
LCXTUN2
R/W-0
LCXTUN1
R/W-0
LCXTUN0
R/W-0
R1PAR
bit 8 Legend: R = Readable bit -n = Value at POR bit 8-7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 0
DATOUT<1:0>: LFDATA Output type bit 00 = Demodulated output 01 = Carrier clock output 10 = RSSI output 11 = RSSI output LCXTUN<5:0>: LCX Tuning Capacitance bit 000000 = +0 pF (Default) 111111 = +63 pF R1PAR: Register 1 Parity Bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits
bit 6-1
bit 0
REGISTER 5-3:
R/W-0
RSSIFET
CONFIGURATION REGISTER 2 (ADDRESS: 0010)
R/W-0
LCYTUN5
R/W-0
CLKDIV
R/W-0
LCYTUN4
R/W-0
LCYTUN3
R/W-0
LCYTUN2
R/W-0
LCYTUN1
R/W-0
LCYTUN0
R/W-0
R2PAR
bit 8 Legend: R = Readable bit -n = Value at POR bit 8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 0
RSSIFET: Pull-down MOSFET on LFDATA pad bit (controllable by user in the RSSI mode only) 1 = Pull-down RSSI MOSFET on 0 = Pull-down RSSI MOSFET off CLKDIV: Carrier Clock Divide-by bit 1 = Carrier clock/4 0 = Carrier clock/1 LCYTUN<5:0>: LCY Tuning Capacitance bit 000000 = +0 pF (Default) : 111111 = +63 pF R2PAR: Register 2 Parity bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits
bit 7
bit 6-1
bit 0
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MCP2030A
REGISTER 5-4:
R/W-0
-- --
CONFIGURATION REGISTER 3 (ADDRESS: 0011)
R/W-0
LCZTUN5
R/W-0
R/W-0
LCZTUN4
R/W-0
LCZTUN3
R/W-0
LCZTUN2
R/W-0
LCZTUN1
R/W-0
LCZTUN0
R/W-0
R3PAR
bit 8 Legend: R = Readable bit -n = Value at POR bit 8-7 bit 6-1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 0
Unimplemented: Read as `0' LCZTUN<5:0>: LCZ Tuning Capacitance bit 000000 = +0 pF (Default) 111111 = +63 pF R3PAR: Register 3 Parity Bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits
bit 0
REGISTER 5-5:
R/W-0
LCXSEN3
CONFIGURATION REGISTER 4 (ADDRESS: 0100)
R/W-0
LCXSEN1
R/W-0
LCXSEN2
R/W-0
LCXSEN0
R/W-0
LCYSEN3
R/W-0
LCYSEN2
R/W-0
LCYSEN1
R/W-0
LCYSEN0
R/W-0
R4PAR
bit 8 Legend: R = Readable bit -n = Value at POR bit 8-5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 0
LCXSEN<3:0>(1): Typical LCX Sensitivity Reduction bit 0000 = -0 dB (Default) 0001 = -2 dB 0010 = -4 dB 0011 = -6 dB 0100 = -8 dB 0101 = -10 dB 0110 = -12 dB 0111 = -14 dB 1000 = -16 dB 1001 = -18 dB 1010 = -20 dB 1011 = -22 dB 1100 = -24 dB 1101 = -26 dB 1110 = -28 dB 1111 = -30 dB LCYSEN<3:0>(1): Typical LCY Sensitivity Reduction bit 0000 = -0 dB (Default) 1111 = -30 dB R4PAR: Register 4 Parity bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits
bit 4-1
bit 0
Note 1: Assured monotonic increment (or decrement) by design.
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REGISTER 5-6:
R/W-0
AUTOCHSEL
CONFIGURATION REGISTER 5 (ADDRESS: 0101)
R/W-0
MODMIN1
R/W-0
AGCSIG
R/W-0
MODMIN0
R/W-0
LCZSEN3
R/W-0
LCZSEN2
R/W-0
LCZSEN1
R/W-0
LCZSEN0
R/W-0
R5PAR
bit 8 Legend: R = Readable bit -n = Value at POR bit 8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 0
AUTOCHSEL: Auto-Channel Select bit 1 = Enabled - Device selects channel(s) that has demodulator output "high" at the end of T AGC; or otherwise, blocks the channel(s). 0 = Disabled - Device follows channel enable/disable bits defined in Register 0 AGCSIG: Demodulator Output Enable bit, after the AGC loop is active 1 = Enabled - No output until AGC is regulating at approximately 20 mVPP at input pins. The AGC Active Status bit is set when the AGC begins regulating. 0 = Disabled - The device passes signal of any level it is capable of detecting MODMIN<1:0>: Minimum Modulation Depth bit 00 =33% 01 =60% 10 =14% 11 =8% LCZSEN<3:0>(1): LCZ Sensitivity Reduction bit 0000 = -0 dB (Default) 1111 = -30 dB R5PAR: Register 5 Parity bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits Assured monotonic increment (or decrement) by design.
bit 7
bit 6-5
bit 4-1
bit 0 Note 1:
DS22235B-page 58
2011 Microchip Technology Inc.
MCP2030A
REGISTER 5-7:
R/W-0
COLPAR7
COLUMN PARITY REGISTER 6 (ADDRESS: 0110)
R/W-0
COLPAR5
R/W-0
COLPAR6
R/W-0
COLPAR4
R/W-0
COLPAR3
R/W-0
COLPAR2
R/W-0
COLPAR1
R/W-0
COLPAR0
R/W-0
R6PAR
bit 8 Legend: R = Readable bit -n = Value at POR bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 0
COLPAR7: Set/Cleared so that this 8th parity bit + the sum of the Config register row parity bits contain an odd number of set bits. COLPAR6: Set/Cleared such that this 7th parity bit + the sum of the 7th bits in Config registers 0 through 5 contain an odd number of set bits. COLPAR5: Set/Cleared such that this 6th parity bit + the sum of the 6th bits in Config registers 0 through 5 contain an odd number of set bits. COLPAR4: Set/Cleared such that this 5th parity bit + the sum of the 5th bits in Config registers 0 through 5 contain an odd number of set bits. COLPAR3: Set/Cleared such that this 4th parity bit + the sum of the 4th bits in Config registers 0 through 5 contain an odd number of set bits. COLPAR2: Set/Cleared such that this 3rd parity bit + the sum of the 3rd bits in Config registers 0 through 5 contain an odd number of set bits. COLPAR1: Set/Cleared such that this 2nd parity bit + the sum of the 2nd bits in Config registers 0 through 5 contain an odd number of set bits. COLPAR0: Set/Cleared such that this 1st parity bit + the sum of the 1st bits in Config registers 0 through 5 contain an odd number of set bits. R6PAR: Register 6 Parity bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits
2011 Microchip Technology Inc.
DS22235B-page 59
MCP2030A
REGISTER 5-8:
R/W-0
CHZACT
STATUS REGISTER 7 (ADDRESS: 0111)
R/W-0
CHXACT
R/W-0
CHYACT
R/W-0
AGCACT
R/W-0
WAKEZ
R/W-0
WAKEY
R/W-0
WAKEX
R/W-0
ALARM
R/W-0
PEI
bit 8 Legend: R = Readable bit -n = Value at POR bit 8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 0
CHZACT: Channel Z Active(1) bit (cleared via Soft Reset) 1 = Channel Z is passing data after TAGC 0 = Channel Z is not passing data after TAGC CHYACT: Channel Y Active(1) bit (cleared via Soft Reset) 1 = Channel Y is passing data after TAGC 0 = Channel Y is not passing data after TAGC CHXACT: Channel X Active(1) bit (cleared via Soft Reset) 1 = Channel X is passing data after TAGC 0 = Channel X is not passing data after TAGC AGCACT: AGC Active Status bit (real time, cleared via Soft Reset) 1 = AGC is active (Input signal is strong). AGC is active when input signal level is approximately > 20 mVPP range. 0 = AGC is inactive (Input signal is weak) WAKEZ: Wake-up Channel Z Indicator Status bit (cleared via Soft Reset) 1 = Channel Z caused a device wake-up (passed 64 clock counter) 0 = Channel Z did not cause a device wake-up WAKEY: Wake-up Channel Y Indicator Status bit (cleared via Soft Reset) 1 = Channel Y caused a device wake-up (passed 64 clock counter) 0 = Channel Y did not cause a device wake-up WAKEX: Wake-up Channel X Indicator Status bit (cleared via Soft Reset) 1 = Channel X caused a device wake-up (passed 64 clock counter) 0 = Channel X did not cause a device wake-up ALARM: Indicates whether an Alarm Timer time-out has occurred (cleared via read "Status Register command") 1 = The Alarm Timer time-out has occurred. It may cause the ALERT output to go low depending on the state of bit 4 of the Configuration register 0 0 = The Alarm timer is not timed out PEI: Parity Error Indicator bit - indicates whether a Configuration register parity error has occurred (real time) 1 = A parity error has occurred and caused the ALERT output to go low 0 = A parity error has not occurred Note 1: Bit is high whenever channel is passing data. Bit is low in Standby mode.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
See Table 5-7 for the bit conditions of the AFE Status register after various SPI commands and the AFE POR.
DS22235B-page 60
2011 Microchip Technology Inc.
MCP2030A
TABLE 5-7: STATUS REGISTER BIT CONDITION (AFTER POR AND VARIOUS SPI COMMANDS)
Bit 8 Condition CHZACT CHYACT CHXACT AGCACT WAKEZ WAKEY WAKEX ALARM POR Read Command (STATUS Register only) Sleep Command Soft Reset Executed(1) 0 u u 0 0 u u 0 0 u u 0 0 u u 0 0 u u 0 0 u u 0 0 u u 0 0 0 u u PEI 1 u u u Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Legend: u = unchanged Note 1: See Section 5.20 "Soft Reset" and Section 5.31.2.4 "Soft Reset Command" for the condition of Soft Reset execution.
2011 Microchip Technology Inc.
DS22235B-page 61
MCP2030A
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
14-Lead PDIP
Example
XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN
MCP2030A-I/P e3 1101256
14-Lead SOIC
Example
XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
MCP2030A I/SL^^ e3 1101256
14-Lead TSSOP
Example
XXXXXXXX YYWW NNN
2030AI 1101 256
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
DS22235B-page 62
2011 Microchip Technology Inc.
MCP2030A
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2011 Microchip Technology Inc.
DS22235B-page 63
MCP2030A
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DS22235B-page 64
2011 Microchip Technology Inc.
MCP2030A
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2011 Microchip Technology Inc.
DS22235B-page 65
MCP2030A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS22235B-page 66
2011 Microchip Technology Inc.
MCP2030A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
2011 Microchip Technology Inc.
DS22235B-page 67
MCP2030A
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS22235B-page 68
2011 Microchip Technology Inc.
MCP2030A
APPENDIX A: REVISION HISTORY
Revision B (March 2011)
The following is the list of modifications: * Updated document templates.
Revision A (January 2010)
* Original Release of this Document.
2011 Microchip Technology Inc.
DS22235B-page 69
MCP2030A
NOTES:
DS22235B-page 70
2011 Microchip Technology Inc.
MCP2030A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact the local Microchip sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) c) Device DSTEMP: Standard VDD range DSTEMPT: (Tape and Reel) DSTEMP-I/P: DSTEMP-I/SL: DSTEMP-I/ST: Industrial Temp., 14LD PDIP. Industrial Temp., 14LD SOIC. Industrial Temp., 14LD TSSOP.
Temperature Range
I=
-40C to +85C
Package
P SL ST
= Plastic Dual In-line (300 mil), 14-lead = Plastic Small Outline (150 mil body), 14-lead = Plastic Thin Shrink Small Outline (4.4 mm, 14-lead
2011 Microchip Technology Inc.
DS22235B-page 71
MCP2030A
NOTES:
DS22235B-page 72
2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in li fe support and/or safety applications is e ntirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-882-5
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
2011 Microchip Technology Inc.
DS22235B-page 73
Worldwide Sales and Service
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
02/18/11
DS22235B-page 74
2011 Microchip Technology Inc.

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